Methods for achieving metal fill in small features

ABSTRACT

A method of electroplating on a workpiece having a sub-30 nm feature generally includes applying a chemistry to the workpiece, the chemistry including a halide ion concentration in the range of about 55 ppm to about 250 ppm and a metal cation solute species, and applying an electric waveform for less than about 5 seconds, wherein the electric waveform includes a period of ramping of current and a period of pulse plating.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional Application No.61/737,044, filed Dec. 13, 2012, the disclosure of which is herebyexpressly incorporated by reference in its entirety.

BACKGROUND

An integrated circuit is an interconnected ensemble of devices formedwithin a semiconductor material and within a dielectric material thatoverlies a surface of the semiconductor material. Devices that may beformed within the semiconductor include MOS transistors, bipolartransistors, diodes, and diffused resistors. Devices that may be formedwithin the dielectric include thin film resistors and capacitors. Thedevices are interconnected by conductor paths formed within thedielectric. Typically, two or more levels of conductor paths, withsuccessive levels separated by a dielectric layer, are employed asinterconnections. In current practice, copper and silicon oxide aretypically used for, respectively, the conductor and the dielectric.

The deposits in a copper interconnect typically include a dielectriclayer, a barrier layer, a seed layer, copper fill, and a copper cap.Conventional electrochemical deposition (ECD) for copper fill and cap isperformed in the feature using an acid plating chemistry.Electrochemical deposition of copper has been found to be the most costeffective manner by which to deposit a copper metallization layer. Inaddition to being economically viable, such deposition techniquesprovide a substantially bottom up (e.g., non-conformal) copper fill thatis mechanically and electrically suitable for interconnect structures.

Conventional ECD copper acid plating chemistry may include, for example,copper sulfate, sulfuric acid, hydrochloric acid, and organic additives(such as accelerators, suppressors, and levelers). The additives drivevoid-free, bottom-up fill in a feature through their adsorptive anddesorptive properties and through competitive reactions, for example, bysuppressing plating at the top and on the sidewalls of the feature,while enhancing plating at the bottom of the feature.

The steady downscaling of interconnect features presents new challenges,because the characteristic dimensions (such as feature width and aspectratio) hinder and alter the reactivity characteristics of additivestypically used. In that regard, sub-30 nm features used for copperinterconnects have small enough volume and require such few copper atomsthat, in a conventional ECD copper acid plating chemistry, the featuresbecome filled within the first few seconds of plating. This is a shortertime period than that required for the adsorption and desorptionkinetics of the bath additives that drive traditional bottom-up filling.

Therefore, in small features (e.g., sub-30 nm features), a conventionalECD fill may result in a lower quality interconnect due to the presenceof voids. As one example of a type of void formed using conventional ECDdeposition, the opening of the feature may pinch off. Many other typesof voids can also result from using the conventional ECD copper fillprocess in a small feature. Such voids and other intrinsic properties ofa deposit formed using conventional ECD copper fill can increase theresistance of the interconnect, thereby slowing the device anddeteriorating the reliability of the copper interconnect.

Therefore, there exists a need for methods of electrochemical depositionfor filling sub-30 nm features from the bottom up, leaving a reducednumber of void regions. Embodiments of the present disclosure aredirected to filling this and other needs.

SUMMARY

This summary is provided to introduce a selection of concepts in asimplified form that are further described below in the DetailedDescription. This summary is not intended to identify key features ofthe claimed subject matter, nor is it intended to be used as an aid indetermining the scope of the claimed subject matter.

In accordance with one embodiment of the present disclosure, a method ofelectroplating on a workpiece having a sub-30 nm feature is provided.The method generally includes applying a chemistry to the workpiece, thechemistry including a halide ion concentration in the range of about 55ppm to about 250 ppm and a metal cation solute species, and applying anelectric waveform for less than about 5 seconds, wherein the electricwaveform includes a period of ramping of current and a period of pulseplating.

In accordance with another embodiment of the present disclosure, amethod of electroplating on a workpiece having a sub-30 nm feature isprovided. The method generally includes applying a chemistry to theworkpiece, the chemistry including a halide ion concentration in therange of about 55 ppm to about 250 ppm and a metal cation solutespecies, and applying an electric waveform, wherein the electricwaveform includes a period of ramping of current for a period of lessthan 100 msecs and a period of pulse plating for less than about 2 secs.

In accordance with another embodiment of the present disclosure, amethod of electroplating on a workpiece having a sub-30 nm feature isprovided. The method generally includes applying a chemistry to theworkpiece, the chemistry including a halide ion concentration in therange of about 120 ppm to about 150 ppm and a metal cation solutespecies, and applying an electric waveform, wherein the electricwaveform includes a period of ramping of current for a period of lessthan 100 msecs and a period of pulse plating for less than about 2 secs.

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the metal cation may be copper.

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the halide ion concentration may be inthe range of about 120 ppm to about 150 ppm.

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the halide ion may be selected from thegroup consisting of chloride, bromide, and iodide ions, and combinationsthereof.

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the ramping of current may be selectedfrom the group consisting of linear continuous ramping, non-linearcontinuous ramping, or pulsed ramping.

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the ramping period may be for a periodof less than about 0.1 seconds (100 msecs).

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the ramping period may begin after adelay period.

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the ramping may achieve a current levelselected from the group consisting of in the range of about 1 amps toabout 15 amps and in the range of about 7 amps to about 15 amps.

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the pulsing period may be for a periodof less than about 2 seconds (2000 msecs).

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the pulsing period may have a dutycycle in the range of about 20% to about 75%.

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the pulsing period may have a dutycycle of about 50%.

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the individual pulses extend for apulse length selected from the group consisting of about 1 msec to about100 msec, about 5 msec to about 100 msec, and about 5 msec to about 50msec.

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the on current pulses may be at acurrent level selected from the group consisting of in a range of about1 to about 30 amps and in a range of about 4.5 to about 30 amps.

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the off current pulses may be at acurrent level in a range selected from the group consisting of about 0amps to about 20 amps, about 0 amps to about 10 amps, and about 0 ampsto about 5 amps.

In accordance with another embodiment of the present disclosure, in anyof the methods described herein, the waveform may further include atriggered hot entry.

DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of thisdisclosure will become more readily appreciated by reference to thefollowing detailed description, when taken in conjunction with theaccompanying drawings, wherein:

FIG. 1 is an exemplary current waveform for use in a copperelectrochemical deposition plating process in accordance with oneembodiment of the present disclosure;

FIG. 2 is an exemplary current waveform for use in a copperelectrochemical deposition plating process in accordance with oneembodiment of the present disclosure;

FIG. 3 is a cross-sectional SEM image of a workpiece after using copperelectrochemical deposition plating process in accordance with oneembodiment of the present disclosure; and

FIG. 4 is a void count comparison for various test substrates subject tovarious test conditions prepared in accordance with embodiments of thepresent disclosure.

DETAILED DESCRIPTION

Embodiments of the present disclosure are directed to workpieces, suchas semiconductor wafers, devices, or processing assemblies forprocessing workpieces, and methods of processing the same. The termworkpiece, wafer, or semiconductor wafer means any flat media orarticle, including semiconductor wafers and other substrates or wafers,glass, mask, and optical or memory media, MEMS substrates, or any otherworkpiece having micro-electric, micro-mechanical, ormicroelectro-mechanical devices.

Processes described herein are to be used for metal or metal alloydeposition in features of workpieces, which include trenches and vias.In one embodiment of the present disclosure, the process may be used insmall features, for example, features having a feature diameter of lessthan 30 nm. However, it should be appreciated that the processesdescribed herein are applicable to any feature size. The dimension sizesdiscussed in the present application are post-etch feature dimensions atthe top opening of the feature. The processes described herein may beapplied to various forms of metal and metal alloy deposition, forexample, in Damascene applications.

It should be appreciated that the descriptive terms “micro-featureworkpiece” and “workpiece” as used herein include all structures andlayers that have been previously deposited and formed at a given pointin the processing. Embodiments of the present disclosure are directed tomethods for void-free, bottom-up fill in small features. In accordancewith one embodiment of the present disclosure, a method includesproviding a chemical-physical driving force to encourage void-free,bottom-up fill in small features. A suitable chemical-physical drivingforce may include increasing the halide ion concentration in the bathand applying a unique entry and early plating electric waveform at thebeginning of the plating process.

In embodiments of the present disclosure, small features describedherein may be sub-30 nm features, sub-20 nm features, features in therange of 10-30 nm, or features in the range of 5-30 nm.

The term “void-free fill” is defined in the art as a feature having areduced void fill so as not to significantly increase the resistance ofthe interconnect or significantly affect yield or performance of theinterconnect. Although features may include a population of voids,whether generated during plating or during later processing conditions,these voids are generally undetectable in a “void-free fill.” In thatregard, the voids are undetectable when examined visually, for example,using an SEM image as seen in FIG. 3. Moreover, the voids areundetectable if the smaller feature achieves comparable performancevalues, for example, yield, resistance, and reliability values, whencompared to a larger feature that has been determined to be acceptablein the industry for its performance achievements, for example, a 45 nmfeature.

The plating bath may be an acid metal damascene plating bath, including,for example, metal ions (such as copper ions in the form of coppersulfate), an acid concentration (such as sulfuric acid) a halideconcentration (such as a chloride ion concentration in the form ofhydrochloric acid), and organic additives (such as accelerators,suppressors, and levelers). It should be appreciated, however, that themethods described herein may apply to other metals besides copper andother types of chemistries besides those having an acid concentration,such as sulfuric acid.

In accordance with embodiments of the present disclosure, the halide ionconcentration in the plating bath is increased by the use of, forexample, increased chloride ion, bromide ion, or iodide ionconcentration, as well as other suitable halide ions, or combinationsthereof.

As a non-limiting example of a suitable halide, increased chloride ionconcentration may be used in the plating bath. Chloride concentration ina traditional plating bath is typically at a concentration of about 50ppm. In accordance with embodiments of the present disclosure, thechloride concentration may be in the range of about 1.1 to about 5 timesthis typical concentration. In one embodiment of the present disclosure,the chloride concentration may be about 3 times the typical chlorideconcentration in a traditional plating bath. In one embodiment of thepresent disclosure, the chloride concentration may be in the range ofabout 120 to 150 ppm. In one embodiment of the present disclosure, thechloride concentration may be in the range of about 55 ppm to about 250ppm.

Plating baths in accordance with embodiments of the present disclosuremay further include optional organic additives, which may be present invarious concentrations depending on the operational conditions of theplating baths. In that regard, because organic additives in conventionalECD copper acid plating chemistry (such as accelerators, suppressors,and levelers) are largely ineffective in plating chemistry for smallfeatures in accordance with embodiments of the present disclosure, someor all of these additives may not be needed, and therefore, may beremoved from the plating bath. However, if larger features are beingplated using the same chemistry bath as the smaller features, then theseadditives must be included in the plating bath to facilitate void-freeplating in the larger features, as will be described in greater detailbelow.

The plating bath may also include complexing agents that are designed tofacilitate copper deposition without requiring some or all of theorganic additives. As a non-limiting example, a suitable coppercomplexing agent may include a chelator, such asethylenediaminetetraacetic acid (EDTA). Other complexing agents known bythose skilled in the art may also be employed.

In combination with the chemical effects of increased halideconcentration in the plating bath, the use of an electric waveform addsa physical component to the chemistry plating bath. In that regard, thewaveform adds kinetic energy in locations inside the feature thatchemistry alone will not affect. Because the feature size is very smalland approximately of the same scale or on the same order as the platingadditive molecules, the plating chemistry does not behave as expected inlarger features. Therefore, the use of a waveform physically manipulatesthe behavior of the molecules during plating. The waveform may be anelectric current waveform or an electric potential waveform.

Although not wishing to be bound by theory, the waveform is believed bythe inventors to decrease the time delays of the effectiveness ofadditives in a small feature. Because the additives are generallyincluded for use in larger features and not particularly useful insmaller features, an increased halide concentration is believed tomitigate any negative effects of the additives in a small feature. Forexample, the increased halide concentration may mitigate the negativeeffects of a suppressor in the small feature, for which its activationtime has been accelerated by the use of an electric waveform.

In accordance with one embodiment of the present disclosure, a suitablecurrent waveform includes a triggered hot entry and a ramped current,followed by a short time period (less than 5 seconds) of pulse plating.In the triggered hot entry, the current is an open circuit until thewafer touches the chemistry, thereby closing the circuit to initiate thestart of the pre-set waveform.

Because the entire workpiece is not all wet at once, a ramping ofcurrent is used to maintain a constant current density in the workpieceduring the wetting stage. The ramping of the current may be performed inone or more ways. Referring to the non-limiting example in FIG. 1, theramping is a steady ramping. In this example, it takes about 150 msecs(from about 0 to about 150 msecs) for the entire workpiece to beimmersed in the chemistry. Referring to the non-limiting example in FIG.2, steady ramping occurs after a short delay and then is held constant.The length of the delay may be dependent on when the power supply istriggered. In this example, steady ramping occurs from about 0.15 toabout 0.40 seconds, and then is held constant from about 0.40 seconds toabout 0.85 seconds.

It should be appreciated that the ramping stage may be a linearcontinuous ramping, a non-linear continuous ramping, or a pulsedramping. In accordance with one embodiment of the present disclosure,the ramping may achieve a current level in the range of about 1 amp toabout 15 amps. In accordance with one embodiment of the presentdisclosure, the ramping may achieve a current level in the range ofabout 7 amps to about 15 amps. In accordance with another embodiment ofthe present disclosure, the ramping may achieve a current level in therange of about 18 amps to about 25 amps. In accordance with anotherembodiment of the present disclosure, the ramping may achieve a currentlevel in the range of about 7 amps to about 25 amps.

In accordance with embodiments of the present disclosure, the rampingperiod may be less than 0.1 seconds, less than 0.2 seconds, less than0.4 seconds or less than 1.0 second.

Although not wishing to be bound by theory, it is believed by theinventors that after the ramping stage, a pulsed waveform can be used toaccount for the transient effects of current when the pulsing is off Inthat regard, it is believed that a pulsed waveform helps to controlvoltage overshoots that affect the chemistry near the wafer.

The pulsing stage is calculated based on the fill time, topography, andarchitecture of the features. The inventors found that pulsing isadvantageous in reducing voids in very small features (e.g., sub-30 nmfeatures). However, pulsing has a negative effect on larger features inthat it tends to create a counter plating effect (for example, bydriving additives away from the plating surface), which results inconformal deposition, as opposed to desired bottom-up (or non-conformal)fill (see, e.g., experimental results described in EXAMPLE 4 below).Conformal deposition is not desirable in larger features because of thetendency to create pinch-off. Therefore, the pulsing stage is limited toa time period in which the sub-30 nm features fill, ending beforenegative consequences are experienced in the larger features.

In accordance with one embodiment of the present disclosure, the pulsingstage may extend for up to 2 seconds (2000 msecs). In accordance withone embodiment of the present disclosure, the pulsing stage may extendfor up to 0.5 seconds (500 msecs). In accordance with embodiments of thepresent disclosure, pulses may be in the range from about greater than 1msec to about 100 msecs in length. In one embodiment, pulses may be inthe range from about 5 msec to about 100 msecs in length. In oneembodiment, pulses may be in the range from about 5 msec to about 50msecs in length. In the illustrated embodiments of FIGS. 1 and 2, thepulses are about 10 msecs in length. (Of note, the pulsing schemeappears as a block from 0.85 to 3.1 seconds in FIG. 2 because of thelimited resolution for the timescale shown.) A non-limiting example of a“long” pulsing scheme may include, for example, a pulsing period of 15seconds, with pulses occurring about every 10 msecs. Pulses length canbe as long as 4 seconds per pulse.

In one embodiment of the present disclosure, current “on” or “high”pulses may be in the range of about 1 to about 30 amps. In anotherembodiment of the present disclosure, current “on” or “high” pulses maybe in the range of about 4.5 to about 30 amps. Current “off” or “low”pulses may be in the range of about 0 to about 20 amps, about 0 to about10 amps, and about 0 to about 5 amps.

The duty cycle of the pulsing stage may be in the range of about 20% toabout 70%, using a maximum duty cycle of 75%. In one embodiment of thepresent disclosure, the duty cycle is about 50%.

The combination of increased halide ion concentration and a specificpattern of electric waveform is generally believed by those skilled inthe art to be counterproductive in an electrochemical depositionprocess. In that regard, increased halide ion concentration is generallybelieved by those skilled in the art to accelerate electrochemicaldeposition in a small features, whereas an electric waveform isgenerally believed by those skilled in the art to suppresselectrochemical deposition.

Although not wishing to be bound by theory, the inventors of the presentapplication believe that the combination of the increased halide ionconcentration and a specific pattern of electric waveform providesadvantageous electrochemical deposition results because of the specifictiming of activities in a small feature. In a non-limiting example,within about the first 100 msecs of plating in a small feature, thepresence of halide ions causes deposition to be accelerated. During thistime period, a suppressing additive present in the plating chemistry haslikely not reached the inside the small feature, and therefore is notyet effective there. However, the suppressing additive may help suppressdeposition outside the feature on the field.

As the small feature begins to fill during this time period, a waveformmay be applied to slow down or suppress deposition. The waveform mayhave a period of ramping so as not to completely suppress theacceleration caused by the increased halide concentration, therebyallowing some deposition in the small feature.

Within about the second 100 msecs of plating in a small feature, asuppressing additive present in the plating chemistry may begin to takeeffect in the small feature. The waveform adds to the suppressioneffects to slow down deposition and reduce the likelihood of voids inthe feature.

After about 1 second, an accelerating additive present in the platingchemistry begins to take effect. Therefore, pulse plating can be used tocontrol the acceleration effects.

As described in the EXAMPLES that follow, void-free fill has beenachieved on a test substrate in the Applied Materials CFD3LM platingchamber, and verified by SEM imaging. Sub-30 nm features on bothinternal and external wafers have been successfully filled and verifiedusing post-CMP defect inspection.

EXAMPLE 1 Exemplary Waveform

An exemplary waveform is provided in FIG. 1 for the first 350 msecs ofplating, showing current ramping at entry for 150 msecs, followed by 10msec, 50% duty cycle pulses. In FIG. 1, about 0.2 seconds (200 msecs) ofpulsing is shown; however, the pulsing scheme can continue for a longerduration. In one non-limiting example, the pulsing scheme may continuefor 0.5 seconds (500 msecs).

EXAMPLE 2 Exemplary Waveform

Another exemplary waveform is provided in FIG. 2 for the first 4 secs ofplating, showing current ramping beginning at 0.15 secs, when the waferis fully submerged in the plating solution. The 10 msec pulses appear asa “block” from 0.85 to 3.1 secs in FIG. 2 because of the limitingresolution for the timescale shown. In FIG. 2, a little over 2 seconds(2000 msecs) of pulsing is shown.

EXAMPLE 3 SEM Image

Referring to FIG. 3, a cross-sectional SEM image showing void-free gapfill with 120 ppm chloride in the plating solution and the platingwaveform of EXAMPLE 2 and FIG. 2.

EXAMPLE 4 Comparative Void Count Results

Referring to FIG. 4, comparative void count results are provided forthree different substrates: Substrate A, a sub-20 nm feature; SubstrateB, a sub-20 nm feature; and Substrate C, a 65 nm feature. Substrate Agenerally has smaller arrays for denser feature population. Substrate Balso has small features, but much larger arrays with less dense spacingof feature population.

Each substrate is exposed to five different conditions: (1) controlconditions of 50 ppm chloride ion concentration and no pulse plating;(2) increased chloride conditions of 120 ppm chloride ion concentration;(3) increased chloride conditions of 120 ppm chloride ion concentrationand pulse plating, for example, in accordance with the scheme of FIG. 1;(4) increased chloride conditions of 120 ppm chloride ion concentration,changed additive conditions of increasing overall bath suppression, andpulse plating with a “long” pulse step, for example, in accordance witha scheme that continues for 15 seconds with pulses occurring every 10msecs; and (5) increased chloride conditions of 120 ppm chloride ionconcentration, changed additive conditions of increasing overall bathsuppression, same as condition (4) above, and pulse plating, forexample, in accordance with the scheme of FIG. 1. The void counts ofthese five conditions are graphically shown in FIG. 4.

The results show that the void counts for Substrate A and Substrate Bdecrease as chloride ion concentration is increased in the plating bath,as seen by comparing the data for condition (2) and the data forcondition (1) control. In addition, the void counts for Substrate A andSubstrate B decrease as chloride ion concentration is increased in theplating bath in conjunction with a pulse plating scheme, as seen bycomparing the data for condition (3) with the data for condition (2).The void counts for Substrate A and Substrate B still decrease with BathB (increased chloride concentration, but changed additive conditions),as seen by comparing the data for condition (4) with the data forconditions (1) and (2), but increase slightly over the void countsachieved under condition (3).

The data for condition (5) as compared to the data for condition (4),the void count for Substrate A decreases and void count for Substrate Bincreases. This change in data may be dependent on the differences inarray size between Substrate A and Substrate B, as discussed above, andthe effects of the length of the pulsing period on substrates havingdifferent array size.

For each specific substrate, a desirable waveform can be optimized;therefore, in some instances, a long pulse step may be more desirableover a shorter pulse step, and vice versa. In addition, for eachspecific substrate a desirable bath additive concentration may bedetermined. Therefore, bath chemistry and waveforms can be optimized foreach individual substrate.

As seen in comparing the data for conditions (3), (4), and (5), voidingincreases in Substrate C (65 nm feature) as pulsing is added(particularly a “long” pulse step, as used in condition (4)), whichindicates that pulsing does not improve bottom-up fill in largerfeatures.

While illustrative embodiments have been illustrated and described, itwill be appreciated that various changes can be made therein withoutdeparting from the spirit and scope of the disclosure.

The embodiments of the disclosure in which an exclusive property orprivilege is claimed are defined as follows:
 1. A method ofelectroplating on a workpiece having a sub-30 nm feature, the methodcomprising: (a) applying a chemistry to the workpiece, the chemistryincluding a halide ion concentration in the range of about 55 ppm toabout 250 ppm and a metal cation solute species; and (b) applying anelectric waveform for less than about 5 seconds, wherein the electricwaveform includes a period of ramping of current and a period of pulseplating.
 2. The method of claim 1, wherein the metal cation is copper.3. The method of claim 1, wherein the halide ion concentration is in therange of about 120 ppm to about 150 ppm.
 4. The method of claim 1,wherein the halide ion is selected from the group consisting ofchloride, bromide, and iodide ions, and combinations thereof.
 5. Themethod of claim 1, wherein the ramping of current is selected from thegroup consisting of linear continuous ramping, non-linear continuousramping, or pulsed ramping.
 6. The method of claim 1, wherein theramping period is for a period of less than about 0.1 seconds (100msecs).
 7. The method of claim 1, wherein the ramping period beginsafter a delay period.
 8. The method of claim 1, wherein the rampingachieves a current level selected from the group consisting of in therange of about 1 amps to about 15 amps, and in the range of about 7 ampsto about 15 amps.
 9. The method of claim 1, wherein the pulsing periodis for a period of less than about 2 seconds (2000 msecs).
 10. Themethod of claim 1, wherein the pulsing period has a duty cycle in therange of about 20% to about 75%.
 11. The method of claim 1, wherein thepulsing period has a duty cycle of about 50%.
 12. The method of claim 1,wherein the individual pulses extend for a pulse length selected fromthe group consisting of about 1 msec to about 100 msec, about 5 msec toabout 100 msec, and about 5 msec to about 50 msec.
 13. The method ofclaim 1, wherein the on current pulses are at a current level selectedfrom the group consisting of in a range of about 1 to about 30 amps andin a range of about 4.5 to about 30 amps.
 14. The method of claim 1,wherein the off current pulses are at a current level in a rangeselected from the group consisting of about 0 amps to about 20 amps,about 0 amps to about 10 amps, and about 0 amps to about 5 amps.
 15. Themethod of claim 1, wherein the waveform further includes a triggered hotentry.
 16. A method of electroplating on a workpiece having a sub-30 nmfeature, the method comprising: (a) applying a chemistry to theworkpiece, the chemistry including a halide ion concentration in therange of about 55 ppm to about 250 ppm and a metal cation solutespecies; and (b) applying an electric waveform, wherein the electricwaveform includes a period of ramping of current for a period of lessthan about 100 msecs and a period of pulse plating for less than about 2secs.
 17. A method of electroplating on a workpiece having a sub-30 nmfeature, the method comprising: (a) applying a chemistry to theworkpiece, the chemistry including a halide ion concentration in therange of about 120 ppm to about 150 ppm and a metal cation solutespecies; and (b) applying an electric waveform, wherein the electricwaveform includes a period of ramping of current for a period of lessthan about 100 msecs and a period of pulse plating for less than about 2secs.